The present invention relates generally to a thin film transistor to be used in matrix type liquid crystal display elements and the like, and a method of manufacturing the same.
FIGS. 5(a) to FIG. 5(d) are sectional views showing a method of manufacturing the conventional thin film transistors.
Referring now to FIG. 5, reference numeral 1 is a glass substrate as a transparent insulating substrate, reference numeral 2 is a gate electrode composed of, for example, Cr provided on the glass substrate 1, reference numeral 3 is a gate insulating film composed of silicon nitride (SiN) formed on the entire face of the glass substrate 1 including the gate electrode 2. Reference numeral 4 is an active layer composed of hydrogenated amorphous silicon (a-Si:H) formed on the gate insulating film 3 corresponding to the gate electrode 2, reference numeral 5 is a protective layer composed of silicon nitride formed on the active layer 4 and having approximately vertical sectional shape. Reference numerals 6 and 7 are source drain regions formed by doping into the hydrogenated amorphous silicon same as the active layer 4 and formed adjacent to both the sides of the active layer 4 by matching with the protective layer 5. Reference numerals 8 and 9 are source/drain electrodes composed of two layers Cr and Al, one portion of which is superposed on the protective film 5 and which is formed, on the source drain regions 6 and 7.
FIG. 6 is a plan view showing the conventional thin film transistor. FIG. 5(d) is a sectional view taken along a line A-A' of FIG. 6. Referring to the drawing, reference numerals 2 and 5 through 9 are the same as those of FIGS. 5(a) to (d). Reference numeral 10 is a chrome silicide formed on the end face of the patterned active layer 4.
FIGS. 7(a) and 7(b) are sectional views showing the conventional thin film transistor. FIG. 7(a) is a section view taken along B-B' of FIG. 6. In the drawing, reference numerals 1 through 5 are the same as those of FIGS. 5(a) to 5(d), reference 10 is the same as that of in FIG. 6. Reference numeral 11 is an etching-removed portion of the protective layer 5.
FIG. 8 is a graph illustrating the gate voltage-drain current characteristics of the thin film transistor and the normal thin film transistor with chrome silicide being formed.
A manufacturing procedure of the conventional thin film transistor will be described hereinafter in accordance with FIG. 5(a) through FIG. 5(d).
The gate electrode 2 is formed by depositing of Cr by a spattering method on the glass substrate 1 and etching of Cr with a given shape of resist as mask (FIG. 5(a)). A trapezoidal sectional shape is obtained with the use of ceric nitrate ammonium, and a mixed liquid of nitric acid and pure water as an etching liquid in the etching operation. After the resist has been removed, 370 nm of silicon nitride film, 100 nm of hydrogenated amorphous silicon film, and 200 nm of silicon nitride film are continuously deposited by a plasma CVD method. The 370 nm of silicon nitride film becomes a gate insulating film 3. Approximately vertical sectional shape of protective layer 5 is formed (FIG. 5(b)) by the plasma-etching using the mixed gas of (CHF.sub.3 and He) after resist has been formed on the uppermost layer of silicon nitride film.
Then, after the resist has been removed, phosphorus is implanted into the entire face of the substrate to form n-type of hydrogenated amorphous silicon film. The active layer 4 which is the hydrogenated amorphous silicon of the non-dope is formed for self-matching operation into the pattern of the protective layer 5, when all the phosphorus ions have been implanted at 11 kV in acceleration voltage, because the phosphorus ion implanted onto the protective layer 5 stays within the protective layer 5. The other region becomes a hydrogenated amorphous silicon (FIG. 5(c) doped into the n type. The n type of hydrogenated amorphous silicon is selectively plasma-etched with respect to the silicon nitride film by freon gas (F123) which is a product of E. I. dupon de Nemour & Co. and a mixed gas between SF.sub.6 and O.sub.2 with resist formed for pattern working the source drain regions 6 and 7, and the protective layer 5 as masks. Thereafter, to form the source drain electrodes, 100 nm of Cr and 300 nm of Al are continuously deposited by a spattering method.
First, the Al is etched with a mixed liquid of phosphoric acid, nitric acid, acetic acid, pure water with resist using in etching of the source drain regions 6 and 7 as masks and is washed sufficiently with the pure water. Then, the etching of Cr is effected with the mixed liquid of ammonium cerium nitrate, perchloric acid, pure water and thereafter the resist is removed. At this stage, the formation of the source drain electrodes 8 and 9 are completed and the conventional thin film transistor is completed.
The conventional thin film transistor and the method of manufacturing the thin film transistor had a problem in that chrome silicide 10 was formed on the end face of the active layer 4 patterned along the profile of the protective layer 5 as shown in FIG. 6, and the off current of such a thin film transistor became higher by few units than the off current (B of FIG. 8) of the normal thin film transistor as shown at A of FIG. 8.
Also, buffered fluorine was conventionally used to remove the chrome silicide 10 with a problem in that the source drain electrodes 8 and 9 were caused abnormal and the disconnection of the wiring was caused in the worst case, because the buffered fluorine was etched even in the Al which was the material of the source drain electrodes 8 and 9.
Also, there was also a method of plasma-etching the substrate entire face with the use of the mixed gas between CF.sub.4 and O.sub.2 as a method of removing the chrome silicide 10. However, the chrome silicide 10 could hardly be removed by the plasma-etching (FIG. 7(b)), because the chrome silicide 10 was formed beneath the protective layer 5 as shown in FIG. 7(a).
The present invention is provided to solve such problems as described above. A first object of the present invention is to remove a conductive layer which becomes a leakage current path between the source drain electrodes such as chrome silicide or the like to be formed on the end face of the active layer to obtain the thin film transistor which does not become high in the off current.
Also, a second object thereof is to provide a method of manufacturing such thin film transistor.
Further, a third object thereof is to provide a thin film transistor where the chrome silicide is hard to form in the end face of the active layer.
Also, a fourth object thereof is to provide a method of manufacturing such a thin film transistor.